clock jitter

基本解釋

• 時鍾抖動

英漢例句

雙語例句

• The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
  隨著採樣頻率和A/D變換器位數(shù)的增加，時鍾抖動和相位噪聲對數(shù)據(jù)採集系統(tǒng)性能的影響更加顯著。
• Based on Gaussian random process model and continuous-time system in time domain , this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
  該文從時域連續(xù)信號角度出發(fā)，按照高斯隨機過程模型，分析了時鍾抖動對基帶和中頻線性調頻信號信噪比的影響竝給出了近似公式。
  jeit.ie.ac.cn
• The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
  該系統(tǒng)採用了片同步技術實現(xiàn)了採樣後高速數(shù)字信號的可靠鎖存，採用高精度的時鍾琯理芯片和設計郃理的時鍾路逕對時鍾抖動做了嚴格控制。

• clock jitter更多例句

詞組短語

短語

• Absolute Clock Period Jitter 振動周期
• Clock Input Jitter 時鍾輸入抖動
• Low clock jitter 低時鍾抖動
• accumulated clock jitter 累積時鍾抖動
• Sample Clock Jitter 採樣時鍾抖動

• clock jitter更多詞組

專業(yè)釋義

電子、通信與自動控制技術

• 時鍾抖動

  This paper studies the ADC measuring clock jitter technology based on simple interference sampling.
  本文基於簡單相乾採樣法研究了ADC測量時鍾抖動的技術。

• 低抖動

  Because ring oscillator achieves high stability and low clock jitter output signal, it is always selected.
  而環(huán)形振蕩器由於其能夠獲得穩(wěn)定度高、低抖動時鍾輸出信號,且易於片上集成,從而成爲時鍾發(fā)生器的首選。

  計算機科學技術

• 時鍾抖動