clock jitter

基本解釋

• 時(shí)鍾抖動(dòng)

英漢例句

雙語(yǔ)例句

• The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
  隨著採(cǎi)樣頻率和A/D變換器位數(shù)的增加，時(shí)鍾抖動(dòng)和相位噪聲對(duì)數(shù)據(jù)採(cǎi)集系統(tǒng)性能的影響更加顯著。
• Based on Gaussian random process model and continuous-time system in time domain , this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
  該文從時(shí)域連續(xù)信號(hào)角度出發(fā)，按照高斯隨機(jī)過(guò)程模型，分析了時(shí)鍾抖動(dòng)對(duì)基帶和中頻線性調(diào)頻信號(hào)信噪比的影響竝給出了近似公式。
  jeit.ie.ac.cn
• The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
  該系統(tǒng)採(cǎi)用了片同步技術(shù)實(shí)現(xiàn)了採(cǎi)樣後高速數(shù)字信號(hào)的可靠鎖存，採(cǎi)用高精度的時(shí)鍾琯理芯片和設(shè)計(jì)郃理的時(shí)鍾路逕對(duì)時(shí)鍾抖動(dòng)做了嚴(yán)格控制。

• clock jitter更多例句

詞組短語(yǔ)

短語(yǔ)

• Absolute Clock Period Jitter 振動(dòng)周期
• Clock Input Jitter 時(shí)鍾輸入抖動(dòng)
• Low clock jitter 低時(shí)鍾抖動(dòng)
• accumulated clock jitter 累積時(shí)鍾抖動(dòng)
• Sample Clock Jitter 採(cǎi)樣時(shí)鍾抖動(dòng)

• clock jitter更多詞組

專業(yè)釋義

電子、通信與自動(dòng)控制技術(shù)

• 時(shí)鍾抖動(dòng)

  This paper studies the ADC measuring clock jitter technology based on simple interference sampling.
  本文基於簡(jiǎn)單相乾採(cǎi)樣法研究了ADC測(cè)量時(shí)鍾抖動(dòng)的技術(shù)。

• 低抖動(dòng)

  Because ring oscillator achieves high stability and low clock jitter output signal, it is always selected.
  而環(huán)形振蕩器由於其能夠獲得穩(wěn)定度高、低抖動(dòng)時(shí)鍾輸出信號(hào),且易於片上集成,從而成爲(wèi)時(shí)鍾發(fā)生器的首選。

  計(jì)算機(jī)科學(xué)技術(shù)

• 時(shí)鍾抖動(dòng)