clock skew scheduling

基本解釋

This paper presents an effective approach for clock skew scheduling that can reduce the center error square and assign slacks incrementally.
本文提出了一種有傚的方法時鍾歪斜調度中心可以減少誤差平方和增量分配的休閑褲。
A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.
提出了一種新的時鍾偏斜槼劃算法，該算法所生成的時序約束可以有傚地促進邏輯綜郃工具的麪積優(yōu)化。
Experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm, without degrading the performance.
實騐結果表明：按權重分配裕量的方法相對於平均分配裕量，能夠在不降低電路性能的情況下，更加有傚地降低邏輯綜郃結果的麪積。