instruction fetch cycle

基本解釋

At per cycle, processor fetch many instruction from many thread to manage operation.
在每個周期，處理機從多個線程取出多條指令調度執(zhí)行。
Another unique architectural feature is the memory system which allows an instruction fetch and at the same time a data access by each individual core at every single clock cycle .
另一個獨特的構架特性是內存系統(tǒng)，它允許一個取指，并在同一時間，每一個核可以讀取數據在每一個單獨的時鐘周期內。