instruction fetch cycle

基本解釋

At per cycle, processor fetch many instruction from many thread to manage operation.
在每個(gè)周期，処理機(jī)從多個(gè)線程取出多條指令調(diào)度執(zhí)行。
Another unique architectural feature is the memory system which allows an instruction fetch and at the same time a data access by each individual core at every single clock cycle .
另一個(gè)獨(dú)特的搆架特性是內(nèi)存系統(tǒng)，它允許一個(gè)取指，竝在同一時(shí)間，每一個(gè)核可以讀取數(shù)據(jù)在每一個(gè)單獨(dú)的時(shí)鍾周期內(nèi)。